1. Field of the Invention
The present invention relates to an electronic device, and more specifically to an electronic scrambler/de-scrambler and related method for generating a scrambling sequence.
2. Description of the Prior Art
Modern communications systems have developed rapidly and become a fixture of the information age. Mobile (or cellular) phones are a prime example of how new technology can change people""s lives. Mobile phones offer an inexpensive and convenient way to stay in touch with family, friends, and colleagues. The popularity of mobile phones has led to widespread use, which has created a demand for new functionality and associated advances in technology.
Recently, industry and standardization groups have developed the code division multiple access specification (cdma2000) for third generation (3G wireless communication systems. The cdma2000 system offers expanded functionality to mobile phones such as capabilities for sending pictures, Internet access, and expanded voice functionality.
A key element in most communications devices, including 3G mobile phones, is a scrambler/de-scrambler. A scrambler encodes data so that it can be safely transmitted. From the base station transmitter path, the channel interleaved symbols are scrambled before being fed into a subpacket symbol selection device. A source unit uses a scrambler to scramble data, and then transmits the scrambled data to a destination unit that uses a similar scrambler to descramble the data. The de-scrambler needs to generate the same scrambling sequence as the scrambler. The subpacket symbol selection selects a scrambled sequence start from an Fk value, wherein k is the subpacket index and the Fk value ranges from 72 to 7776 in steps of 24 (i.e. 72, 96 . . . 7752, 7776). According to cdma2000, the Fk value depends on a host of parameters including: an index of a subpacket being scrambled, a number of bits in an encoder packet (a plurality of subpackets), a number of 32-bit Walsh channels indexed by subpacket, a number of 1.25 ms slots for a subpacket, and a modulation order of each subpacket. All of these parameters and how they correlate are well known to those working in the cdma2000 field and are prescribed by the relevant cdma2000 specifications. If an unintended destination unit receives the scrambled data, it is likely that the unintended destination cannot readily descramble or understand the data. Encrypting data using a scrambler serves to protect privacy and commercial interests of data transmissions.
Consider a typical 17-tap linear feedback shift register 10 as shown in FIG. 1 that is used in a forward packet data channel (F-PDCH) of cdma2000 as a scrambler to generate a scrambling sequence. The scrambler 10 comprises a series of connected registers D1-D17 and an exclusive OR (XOR) gate 12 connected to outputs of the registers D14 and D17. Output of the XOR gate 12 is input into the register D1 providing feedback giving the scrambler 10 a generator sequence of h (D)=D17+D14+1. After the registers D1-D17 have been set with an initial state, the scrambler is clocked so that the D17 register outputs the scrambling sequence. The scrambler sequence is used to encode data bits of a communications signal, which in the case of the F-PDCH of cdma2000 means XORing the scrambling sequence with interleaver output symbols.
For the F-PDCH of cdma2000 the operation of the scrambler 10 is as follows. The scrambler 10 is first initialized to an initial state of [D17 . . . D1]=[1b15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0]where the b15, b14, b13, b12, b11, b10, b9, b8, b7, b6, b5, b4, b3, b2, b1, and b 0 bits are from a long code mask prescribed in the cdma2000 specification. That is, register D17 is set to xe2x80x9c1xe2x80x9d, register D16 is set to b15, and so on with register D1 being set to b0. Next, the scrambler 10 is clocked a number of times to generate a scrambling sequence at the output of the register D17. A de-scrambler using the same 17-tap linear feedback shift register 10 must be clocked between 72 and 7776 times to properly set the states of the registers D1-D17 for a particular subpacket. Once this state is reached, the de-scrambler is clocked repeatedly to output the desired scrambling sequence, being the same as that of the scrambler 10.
When the de-scrambler is being clocked by the Fk value it is in a non-performing mode. Naturally, slower overall performance caused by this is more pronounced with higher Fk values. Slower performance of the de-scrambler affects the entire surrounding system and can introduce bottlenecks into otherwise streamlined systems. As it is desirable to avoid delay and increase data transfer rates in mobile phones and other communications systems, the scrambler as described above lacks efficiency. Prior art solutions to this problem include increasing the clock speed of the scrambler, which tends to introduce errors into a transmission.
It is therefore a primary objective of the claimed invention to provide a scrambler and related method that can quickly step though a sequence of unnecessary intermediate states to solve the problems of the prior art.
Briefly summarized, the claimed invention includes an X-tap linear feedback shift register having X registers, a multiplexer having outputs connected to the registers of the X-tap linear feedback shift register, and a plurality of logic gates connected to inputs of the multiplexer defining a generator sequence. Through the multiplexer, the plurality of logic gates provide parallel input to the X-tap linear feedback shift register that allows for an n-step shift operation of the X-tap linear feedback shift register. Also through the multiplexer, the X-tap linear feedback shift register can perform a single shift operation and can be loaded with a predetermined state.
According to the claimed invention, a method provides a series-parallel linear feedback shift register capable of performing a single step shift operation, performing an n-step shift operation, and being loaded with initial values. The method further loads the series-parallel linear feedback shift register with initial values, performs a predetermined number of n-step shift operations with the series-parallel linear feedback shift register, and performs a predetermined number of single step shift operations with the series-parallel linear feedback shift register. The method finally outputs contents of the series-parallel linear feedback shift register as the scrambling sequence while performing at least a portion of the predetermined number of the single step shift operations.
It is an advantage of the claimed invention that the multiplexer offers the X-tap linear feedback shift register three-mode functionality so that the shift register can be initialized, shifted by n-steps, and the shifted by a single step.
It is a further advantage of the claimed invention that a desired point in the generator sequence can be reached more quickly in proportion to the size of the n-step shift operation.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.